The use of chemical-mechanical polishing (CMP) as a planarization technique in VLSI process technology is increasing rapidly. However many of the planarizing applications are directed toward interconnect dielectric planarization for triple-level metal (TLM) and quadruple-level metal (QLM) schemes. Interest in CMP as a tool for use in shallow trench isolation is much more limited because of the dishing effect in nide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss the status of our planarization technique, aimed at the development of a viable shallow trench isolation process for a CMOS technology. We discuss the initial effort which optimizes the planarizing characteristics of our polish process as a function of feature geometry, nitride overcoat, and nitride polish stop. It is shown that large and small features on a variety of mask layouts are planarized simultaneously without dishing. Small features are planarized quickly and remain protected by a nitride polish stop : larger features planarize more slowly and end on the nitride polish stop as well.