Magnetoresistive random access memory has many desirable characteristics compared to other nonvolatile memory technologies. These include no inherent wear-out mechanism, very fast switching capability, and relatively few mask layers required for fabrication. We have investigated sub-micron memory cells patterned from asymmetric giant magnetoresistance (GMR) sandwich materials that have 6%-7.5% signal levels, exhibit sharp single-domain-like switching thresholds, and are sensed in a mode that yields a differential output signal effectively twice the intrinsic GMR of the material. The cell is designed so that the thinner of the two magnetic layers reverses freely in a read operation, while the bit state is stored in the thicker magnetic layer whose magnetization switches only upon writing the bit. Due to the high signal level and similarity in transfer characteristic to that of pinned spin valve material, we have labeled this cell structure and mode of operation pseudo spin valve (PSV). Experimental PSV memory cells and test structures approximately 0.3 mu m in width were patterned and tested, and yielded GMR values of up to about 7.5%. Dependence of the write thresholds on sense line current as well as word and bias line fields was studied and confirmed that two-dimensional cell selection may be used in an array. Single bits exhibited sharp, single-domain-like write threshold characteristics, if properly shaped. Using a single domain model that takes into account static torques on the magnetic layers in a bit, as well as coupling between these layers, transfer curves and switching characteristics that qualitatively match the experimental data were generated. Using the model, properties of conceptual double pseudo spin valve (DPSV) cells were also studied. A DPSV cell is comprised of GMR material with three magnetic layers, where either the center layer or one of the two outer layers acts as the storage film. Advantages of DPSV cells include nearly twice the GMR compared with a PSV cell of similar area, as well as lower write thresholds.