Besides plasma etching of through-wafer interconnects in wafer stacks: for vertical integration of chips [M. Engelhardt et al., Proceedings of the 23rd Annual Tegal Plasma-Seminar (1997)] fabrication of Pt storage nodes with nontapered sidewalls is one of the most challenging tasks of plasma process technology today. In this work the fabrication of vertical Pt profiles was achieved by plasma processing with resist mask. In this novel approach, the buildup of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the preetch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.