Direct write electron-beam lithography is the most flexible technique for sub-0.25 mum imaging in an advanced development environment. The resolution and custom exposure capabilities of electron-beam lithography, as well as the rapid turnaround for new device designs, provide early device/technology feasibility demonstration, learning, and proof-of-concept not easily obtainable with other lithographies. We have used a 50 kV shaped-beam system for advanced complementary metal-oxide-semiconductor (CMOS), bipolar, BiCMOS, and DRAM device prototyping as well as for front-end and back-end process development, metrology standard fabrication, exploratory device fabrication, and x-ray mask fabrication. The high throughput, as compared to vector scan systems, of shaped-beam electron-beam lithography was found to be essential in satisfying the requirements of advanced development programs. The key to success has been a complete understanding and integration of the interaction of the resist process, tool, proximity correction, and metrology at 0.25 mum and below. In this article, we will describe the processes used to obtain minimum dimensions down to 0.1 mum in negative and positive resists with 3sigma linewidth variation typically better than 0.025 mum. Accurate and precise scanning electron microscopy metrology will be shown to be critical for process development and inspection of device wafers. In addition, tool set-up techniques and proximity correction for sub-0.25 mum lithography will be discussed. Working room temperature CMOS devices and circuits, with physical gate widths as small as 0.1 mum, have been fabricated using e-beam lithography for the critical gate level and optical lithography for all other levels. A mixed lithography approach was found to be the most effective use of the e-beam, lithography capabilities.