We report on a dry etch process for backside through-wafer via hole fabrication in InP-based transistors which addresses many manufacturing issues including wafer mounting schemes, degradation of the frontside ohmic metal pads, yield across two-inch wafers, and reliability issues. Low pressure electron cyclotron resonance plasma etching using a CH4/H-2/Ar/Cl-2 gas chemistry is investigated and compared to other InP via etching techniques. A photoresist mask was used to define 54 mu m X 54 mu m backside vias in substrates thinned to similar to 50 mu m. Post-baking the resist served both to strengthen the mask against the plasma, and to control the profile of the through-via. The etching was performed at a temperature of 130 degrees C to enhance etch product volatility while allowing a reliable wax-mounting scheme for the thinned wafers. Etch rates of similar to 1 mu m/min were obtained for 950 W microwave power and 250 W rf power (-260 V). After similar to 95% of the etched depth was achieved, the rf bias was reduced to minimize sputtering of the frontside metal pad on which the etch terminates. After the residual resist mask was removed, the samples were metalized, de-mounted, and tested for electrical connection, resulting in high yield via etching across the wafer.