The deposition of metallic patterns on the surface of a semiconductor is a critical part of today’s very large scale integrated technology, where the patterns are employed in three distinct capacities : as ohmic contacts, as electrostatic gates, and as interconnects. Whereas the feature size of electrostatic gates has been successfully reduced to 20 nm or less, nanostructures have not previously benefited from similar reductions in scale of the ohmic and interconnect technologies. We describe the fabrication and low-temperature investigation of nanostructures defined by submicron-sized gates, interconnections, and ohmic metallization constructed on the surface of AlGaAs/GaAs heterostructures. A two-level metallization is adopted : ohmic and gate surface patterns are linked by patterned interconnects separated by an interlayer insulator. The approach features electron-beam lithography with a +/- 10 nm alignment accuracy and has been used to interconnect several isolated metal patterns as small as 100 nm allowing a new generation of nanostructure designs to be realized. For ohmic metallization we report data from a gated micron-sized Corbino disk-the first example of a nanostructure defined by ohmic contacts incorporating a Schottky gate.