During epitaxial lateral overgrowth of single-crystal silicon over thermal SiO2, in the low-pressure chemical vapor deposition reactor environment, thinning and even pinholes can occur in the underlying gate oxide of in dual-gated silicon on insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). The epitaxial lateral overgrowth was grown using dichlorosilane (DCS), HCl, and H-2 at 970 degrees C and 40 Torr. Although the etch rate was very small, the thinning was large enough to change the bottom channel threshold voltage (Vt). Oxide thickness measurements, obtained by ellipsometry and by profilometer measurements, indicated an etch rate of about 0.1 nm/min, which was independently confirmed from MOSFET Vt shift measurements. The oxide etch rate decreased with increasing concentration of HCl and was less for oxides grown from heavily arsenic-doped than from lightly doped boron silicon.