The formation of dimple/pit on gate oxide and Si substrate was observed after WSix/poly-Si gate stack etch. The effects of process step on the formation of dimple/pit have been studied. The key process steps causing the dimple/pit problem are the WSix anneal and the low pressure chemical vapor deposition nitride deposition. The mechanism of dimple/pit has been proposed. The rough WSix/poly interface is the main cause of dimple formation, and the presence of Si clusters in the annealed WSix layer is the key contributor for pits in the Si substrate. A low temperature process (before gate stack etch) was found to be effective to reduce and/or eliminate the dimple/pit problem.