A reliable small metal contact (MC) process is developed for the gigabit scaled dynamic random access memories (DRAMs). The high aspect ratio contact etch was accomplished by using a high density inductively coupled plasma reactor. The low contact resistance of the MC for the, gigabit scaled DRAMs is realized when the amount of Si consumption at the bottom of the contact holes is minimized (<20 nm). The dopant activation of the source and drain (S/D) regions is also critical to have low contact and sheet resistances (R-c and R-s). Use of the high temperature (>950 degrees C) rapid thermal annealing enhances the dopant activation and effectively reduces the R-c and R-s. Surface treatment of the bottom of the contact hole after dry etch, becomes a key factor to have low contact resistance in the case of small contacts. The conventional Ar+ in situ sputter cleaning deteriorates the contact resistance of the vertically sloped small MCs. Light etch using CF4 and O-2 gases removes damaged layer and improves contact resistance. Rapid thermal nitridation after TiN barrier metal deposition also improves electrical properties of the MCs.