We have developed a simple, trilayer lift-off process for obtaining metal of various thickness while retaining good feature definition down to 1 mu m, using only standard photoresist and developer, and e-beam evaporated dielectric. This process has been implemented for fabrication of high speed circuits using InP/InGaAs/InP double heterojunction bipolar transistor devices. This structure is nonplanar, with a topography of about 1.3 mu m from the top of the emitter to the substrate level for interconnects. Clean edges are obtained for all of the metallization steps. Metal lift-off with our trilayer process is easily accomplished by gentle rinsing with acetone, and does not require the use of high pressure spray or any heat treatment, such as boiling in a solvent to aid lift-off. This new process has greatly improved our circuit yield.