For complementary metal-oxide-semiconductor (CMOS) technology to meet the demanding I scaling requirements for ultrashallow junctions and the low contact resistivity necessary for device fabrication below the 100 nm technology node, significant technological barriers will need to be overcome. Numerous solutions have been proposed and a considerable amount of research and development is currently in progress to determine which, if any, of the proposed processes can provide a definitive cost-effective solution that simultaneously meets all CMOS source and drain requirements. In this article, we present a brief overview of some of the techniques that have been proposed for ultrashallow junction and low contact resistance formation and that are. currently at the forefront for front end of line (FEOL) consideration. The current status of each potential technological solution is reviewed and we will highlight the advantages and disadvantages associated with each. The FEOL process areas that we will restrict our discussion to include conventional and alternative doping and annealing techniques. Our goal is to indicate the current status of the research and development of these novel techniques for the formation of ultrashallow junctions and low resistivity contacts and to indicate the barriers that must be overcome in each process to make it a viable, cost effective technique.