A low temperature (T = 420 degrees C) Al planarization process is demonstrated for filling 0.45 mu m vias with an Aspect Ratio (A.R.) of 2.6, in 0.35 mu m BICMOS process. The thermal budget is a key factor for back-end integration, especially as it dictates type of dielectric-SOG planarization to be used and also the TiN barrier requirements for junction leakage. A detailed integration of process steps governing the Al-plug process, specifically via profiles tailored by sputter etch, enhanced barrier/wetting layer (Ti/TiN), SOG degas, Al deposition conditions (Temperature, Deposition rate) was performed. The vias were characterized electrically (10 K via chain), and by SEM cross-section for 0.45-0.65 mu m geometries, A.R. = 2-3, and variable via spacings.