An overview of the development of advanced Ti and Co self-aligned silicide (SALICIDE) processes for deep-sub micron high performance CMOS technologies at Texas instruments is presented. SALICIDES are a key factor for scaling of high-performance CMOS devices. They are used to lower sheet resistance of gate and source/drain regions, contact resistance and source/drain series resistance, increasing device performance and lowering RC delays to allow faster operation. Their applicability to deep-sub-micron technologies is determined by the fundamental materials aspects controlling silicide phase formation and evolution, as well as process integration issues such as effect of subsequent processing steps on the silicide films or effects of silicide related process steps on transistor characteristics. The main scaling issues for conventional processes, high resistivity on narrow lines for Ti SALICIDE and high diode leakage on shallow junctions for Co SALICIDE, are addressed. Detailed kinetic studies of the high resistivity to low resistivity phase transformations (TiSi2 C49 to C54 and CoSi to CoSi2) and their dependence on Linewidth and film thickness are presented. A nucleation density model is shown to account for the measured linewidth dependence and effect of pre-amorphization implants on the TiSi2 C49 to C54 transformation and explain, as a result, narrow line sheet resistance. This overview covers studies on rapid thermal processing (RTP) for Ti and for Co SALICIDE, pre-amorphization implants and Mo impurities which allowed the first demonstration of low resistivity Ti SALICIDE at 0.10 mu m gate lengths, as well as applications to sub-0.18 mu m CMOS technologies and integration issues.