Measurements indicate that in power conditioning circuits using SiC gate turn-off(GTO) thyristors, conduction losses can be reduced by injection of a portion of the load current through an electrode connected to the base regions so that it encounters only two back-to-back p-n junctions. Simulations of SiC GTO thyristors indicate that the maximum voltage blocked can be increased and the turn-off time reduced by an increase in the thickness of the p-type buffer layer (p+ base region). These simulations also show that it is permissible to have the drift region n-type whether the gates are on an n-base or ap-base. This option is desirable because high-quality thick n-type epilayers are easier to grow than p-type epilayers.