A detailed comparison of the passivation quality and its dependence on the low and high temperature anneals is presented for various promising Si surface passivation schemes. The passivation schemes investigated in this study include: conventional furnace oxide (CFO), rapid thermal oxide (RTO), belt line oxide (BLO), plasma deposited oxide (PDO), SiN deposited by plasma enhanced chemical vapor deposition (PECVD), CFO/SiN, RTO/SiN, BLO/SiN, PDO/SiN, and RTO/PDO. Passivated low resistivity (1 Ohm cm) p-type silicon samples were subjected to three annealing treatments: (a) 400 degrees C in forming gas (FGA), (b) 730 degrees C in air, and (c) 850 degrees C in air, to simulate heat-treatments, which are typically used for contact anneal, front ohmic contacts, and back surface field formation, respectively, for screen printed silicon solar cells. It is found that the passivation quality of PDO, SiN, RTO, and CFO single layers improves significantly after the 400 degrees C FGA and 730 degrees C thermal cycles with RTO resulting in the lowest surface recombination velocities (S-eff) of 154 and 405 cm/s, respectively. Silicon wafers coated with belt oxide (BLO and BLO/SiN) did not show any improvement in S-eff, which remained at 5000 cm/s due to the inferior quality of BLO formed in compressed air. The oxide/ nitride stack passivation is found to be far superior to single-layer passivation resulting in S-eff Of 70 cm/s for the RTO/SiN scheme after the two high temperature anneals (850 and 730 degrees C). The hydrogen concentration measurements by Fourier transform infrared spectroscopy show a greater decrease in the hydrogen content in the annealed RTO/SiN stack compared to the as-deposited SiN single layer after the 730 and 850 degrees C anneals. A combination of reduced hydrogen content and very low S-eff in the RTO/SiN stack suggests that the release of hydrogen from SiN during the anneal further passivates the RTO/Si interface underneath.