Scattering with angular limitation in projection electron-beam lithography (SCALPEL) marks for alignment and registration have been fabricated in SiO2 deposited in Si trenches using a process that is similar to that used for shallow trench isolation in complementary metal-oxide-semiconductor (CMOS) integrated circuits. The marks were detected using backscattered electrons in a SCALPEL exposure tool using 100 keV incident electrons. The signal-to-noise from the Si/SiO2 marks is comparable to that measured from Si/WSi2 marks fabricated in CMOS gate material. The Si/SiO2 marks fabricated from this process are a viable option for gate alignment to the thin oxide level and is extensible to circuits with critical dimensions less than 100 nm.