Relaxed SiGe-on-insulator (SGOI) was fabricated using a bond/etch-back process. Ultrahigh-vacuum chemical vapor deposition was used to grow a SiGe graded buffer on a Si substrate, creating a relaxed Si0.75Ge0.25 Virtual substrate. The SiGe graded buffer surface was then polished, and a second ultrahigh-vacuum chemical vapor deposition growth was performed to deposit a strained Si etch stop layer followed by a Si0.75Ge0.25 layer. The wafers were bonded to oxidized Si handle wafers, and the wafer pairs were annealed. The backsides of the SiGe virtual substrates were ground and etched in KOH. Since the KOH etch stops at the 20% Ge region in the graded layer, the remaining SiGe was then removed using a HF:H2O2:CH3COOH (1:2:3) solution. The resulting SGOI structure was characterized using transmission electron microscopy and atornic force microscopy; in addition, etch-pit density measurements revealed a threading dislocation density of about 105 cm(-2).