Pittings are originated from crystal originate particles. It is difficult to avoid pittings by improving in-line processes. We have measured the amount of defects in both Czochralski (CZ) and epitaxial (EPI) wafers, which were processed by active area etching. For CZ wafers, 27% of total defects were found to be pittings, but only 5.9% for EPI wafers. These pittings may result from the crystal growth and could be further enhanced by dry etching and wet cleaning processes. Standard 0.25 mum standard random access memory (SRAM) fabrication processes were performed on both types of wafers, and electrical tests were carried out to verify the influence of pittings on the device performance. It was found that pittings induced greater leakage current between two adjacent p transistors, which may be due to local thinning at pitting location within the isolation region. However, the pitting induced leakage current was still in an acceptable level, and therefore these pittings with the size as large as 0.2 mum did not have a significant impact on device performance of 0.25 mum SRAM.