We present a simple and high-precision process technology for ultrafast InP-based high electron mobility transistors (HEMTs) having an asymmetrically recessed T-shaped gate. This technology is beneficial in fabricating high-performance InP-HEMTs because it enables us to independently optimize source-and drain-side recess lengths (L-rs, L-rd) while using a very short gate length (L-g). The process utilizes a conventional trilayer resist exposed by electron beam lithography, which has additional slit patterns beside a gate-foot pattern in the bottom layer. The gate metal is evaporated at a tilted angle to avoid evaporation through the slit patterns. The Lrs and Lrd can be precisely controlled by the etching time, and by the size and position of the slits, while keeping a constant recess depth. A 60 nm gate HEMT with a longer L-rd exhibits a much-enhanced maximum oscillation frequency (f(max)) of 428 GHz mainly by reducing the drain conductance (g(d)) and the gate-to-drain capacitance (C-gd), as compared to that (244 GHz) for a conventional HEMT with a symmetric recess structure.