As the density of dynamic random access memories (DRAMs) enters into giga-bit regime with deep sub-quarter-micrometer feature size, the control of junction leakage current at storage node becomes much more important because of increased channel doping concentration. In this paper, we analyzed the junction leakage current of cell transistor and suggested effective cell structure to improve the data retention time for mass-produced 512 Mb DRAM with 0.12 mum. This cell structure, which is based on localized channel and field implantation, reduces the junction leakage current by relaxing junction doping profile and implantation damages at source and drain regions. The relaxed junction profile can reduce the electric field strength of a junction and thus improve data retention time in DRAMs. In addition, subthreshold characteristics of a cell transistor are improved dramatically with this scheme by increasing threshold voltage of corner transistor that is generally lowered by boron segregation and field crowding at the shallow trench isolation boundary in the conventional cell transistor. The proposed approach reduced the cumulative fail-bit probability by about 80% at the data retention time of 128 ms and possibly, can be applied to future high density DRAMs with feature size down to 0.1 mum range. (C) 2003 The Electrochemical Society.