Copper indium disulfide cells fabricated on a continuous copper tape fabricated at IST (D) are continuously improving, now reaching efficiencies above 9%, with V-oc exceeding 650 mV, and fill factors well above 65%. The internal structure of these cells, however, is complicated, and far away from that of an ideal flat and homogeneous crystalline cell: in the depth, there is a sequence of several different layers, which is inherent to this technology; also, lateral inhomogeneities cannot always be precluded. An admittance study was undertaken to characterize the internal electronic cell structure. We carried out C(V,f,T) measurements, i.e. capacitance and conductance vs. voltage and vs. frequency, at temperatures varying between 80 and 300 K. Maxima are observed in the C-V curves at high forward bias voltage. C-f and G-f measurements are interpreted in terms of deep states. The internal consistency of the interpretation of various measurements is validated with numerical simulation (SCAPS proaramme). (C) 2003 Elsevier B.V. All rights reserved.