The interface propel-ties of a-SM/c-Si heterojunction solar cells fabricated with different pre-treatments (tunnel oxide formation or HF dip) of the p-doped c-Si wafers and different thickness of n-doped a-Si:H layers were investigated by admittance and transport measurements. Depending on the wafer treatment, we observe either one or two capacitance steps in the capacitance vs. temperature (C-T) curve, that are accompanied by one or two peaks in the conductance vs. temperature (G-T) curve. For the sample with HF dip treatment and an a-Si:H thickness below 10 nm, no capacitance step at all could be observed. The C-T and G-T curves were correlated to the current-voltage characteristics under illumination and to the solar cell performance. Heterostructures showing a step on the C-T curves also show S-shape I-V curves under illumination at low temperature. (C) 2003 Elsevier B.V. All rights reserved.