By forming physically separated 30 nm twin ONOs with an inverted sidewall spacer patterning method under a single gate based on damascene gate process, problems of the charge distribution and diffusion during and after the channel hot electron injection program in the 2-bit operation of the localized trap memory were cleared out. The two charge storage nodes of nitride with length of 30 nm under the 100 nm channel length can be created by adopting inverted amorphous polysilicon spacer and inner offset oxide process made in the groove. This inverted amorphous silicon spacer process does not suffer from unit-cell size increase, photoresolution limit, nor photo misalign between gate and oxide-nitrogen-oxide structures. In addition, the inner offset oxide protects the ultrathin amorphous Si spacer from the loss due to the subsequent etch process and plays an important role of minimizing the overlap between gate and source/drain. In this structure, the spatial distribution can be controlled and lateral charge diffusion is blocked, so that stable 2-bit operation with high erase speed and reliabilities such as endurance and retention can be achieved, compared with the conventional single silicon-oxide-nitride-oxide-silicon structure under 100 nm regimes. (C) 2004 American Vacutan Society.