Low-energy electron projection lithography (LEEPL) is a candidate for next generation lithography and thus the 1 X LEEPL mask requires a stringent local image placement (IP) error budget. Applying a doping method with silicon-on-insulator substrates, 700-nm-thick membranes were investigated for stress control and in-plane distortion (IPD), which are the main contributors to local IP errors. Stress control results show that at a dopant concentration of 6.74 x 10(19)/cm(3). the membrane stress in a 10 mm test structure is 8.4 MPa. Also stress variation is excellent at 0.3 MPa across a 200 mm complementary stencil mask on support strut-type LEEPL mask. The IPD results indicate that small membrane window size, low void fraction, as well as low membrane stress is the proper strategy to allow a stencil mask with dense stencil patterns to meet required IPD. Additionally, the local IP errors of large scale integrated 90 nm hole pattern were demonstrated. (C) 2004 American Vacuum Society.