Monolithic integration of different electronic circuit elements onto a single chip is beneficial for the purpose of reducing overall system cost as well as improving performance and reliability. Integrating a power unit onto a silicon chip requires the implementation of a thin-film solid-state battery that is compatible with existing silicon integrated circuit technology in terms of manufacturing methods, materials, and performance. One of the materials in the battery industry, studied by us, is silicon dioxide (SiO2). The high level of process control for thin SiO2 layers which is a result of microelectronic advances, its insulating properties, and its past reported permeability to light ions have motivated us to exploit SiO2 as a solid-state electrolyte in our integrated thin-film battery. This SiO2 electrolyte layer is thermally grown from an amorphous silicon (a-Si) thin layer deposited on doped polycrystalline silicon (polysilicon) which serves as the anode against a thin-film-sputtered LiCoO2 cathode. We have fabricated and characterized ultrathin solid-state thin-film power cells consisting of LiCoO2, SiO2, and polysilicon. Cells containing an ultrathin SiO2 lithium-free electrolyte with a thickness range of 7-40 nm and active-area sizes of 5 X 5, 2 X 2, 1 X 1, and 0.5 X 0.5 mm(2) were created using established microelectronics processing and expertise. Ultrathin cells require smooth surfaces (nanometer-scale roughness) as opposed to higher roughness encountered in bulk batteries and microbatteries. To ensure a very thin and flat electrolyte, this work demonstrates the implementation of a planarization step by using chemical mechanical polishing (CMP) in the fabrication of the integrated solid-state thin-film lithium-ion battery. Polishing the polysilicon layer reduced its 1 X 1 mu m(2) root-mean-square roughness from 8.06 to 0.53 nm and led to smoother interfaces and to higher quality of the SiO2 grown on top of it. The cells were charged and discharged using conventional microelectronic electrical testing equipment and exhibited improved performance when prepared with the additional CMP planarization step. Up to 40% of the charge was retrieved from the planarized cells compared to a maximum of 14.5% retrieved from the nonplanarized cells. The open circuit voltage (V-OC)(-) of the LiCoO2/SiO2/polysilicon cell was estimated by comparing the initial charge voltage values obtained with different electrolyte thicknesses and was found to be 2.19 +/-0.02 V. The results presented in this work show the importance of interfacial quality in the process of moving to integrated power on a chip. (c) 2006 American Vacuum Society.