The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 mu m gate length strained Si/Si0.75Ge0.25 CMOS technology has the same gate delay as conventional technology having an effective gate length of 0.14 mu m, but without the cost of re-tooling. Transconductance enhancements over conventional CMOS in excess of 200% are demonstrated for surface channel n- and p-MOSFETs using a Si0.75Ge0.25 virtual substrate without CMP and a high thermal budget process. To our knowledge these represent the best results reported to date at these dimensions. (c) 2005 Published by Elsevier B.V.