This work presents a reproducible, super-self-aligned approach for fabricating back-gate/double-gate transistors with a thin silicon channel and thick doped source/drain polysilicon access regions. Such a device structure can lead to ultimate electrostatic control of the channel without sacrificing source/drain series resistance in a deeply scaled field effect transistor. The approach consists of a unique combination of silicon complementary-metal-oxide-semiconductor front-end processing techniques, along with wafer bonding, sidewall spacer formation (in oxide and nitride), solid-state junction diffusion, and multistage chemical mechanical polishing for wafer-level planarization. The authors further demonstrate the formation of a reliable contact at the source/drain junction interface between doped polysilicon and the undoped silicon channel. In the design, through oxidation, the authors are able to introduce strain in the structure, as well as buried interconnects in a plane below the device. Both n-channel and p-channel devices have shown high drive currents, strong back-gate coupling, and high effective carrier mobility. (c) 2006 American Vacuum Society.