The paper presents the results of improved feedback charge capacitance-voltage (C-V) measurements obtained on a porous silicon (PS)/p-type crystalline silicon (c-Si) structure prepared in the MOS configuration. Even though the porosity (less than 10%) of the similar to 1-mu m-thick PS overlayer is low, some electrical properties of the structure are considerably sensitive to the light exposure. Such parameters as Fermi level position, flat-band voltage, surface potential, positions of the deep-level hole traps and acceptor density will be presented for various situations as defined by the sample ambient, the temperature and light illumination. The following two findings are shown and analyzed: (i) total suppression of the large hysteresis, which is typical for the measurements in dark, of the C-V curves after the illumination, and which is related to the Staebler-Wronski effect (SWE); (ii) interface states are recovered in the dark and its density N-ss has increased by similar to 4.7 x 10(10) cm(-2) eV(-1) in comparison with the zero density of illuminated PS/c-Si structure.