Strained-Si-on-insulator (strained-SOI) CMOS is a promising device structure for satisfying requirements of both high current drive and low supply voltage under sub-100 nm nodes, because of the combination of advantages of SOI MOSFETs and high mobility strained-Si channels. In this paper, we present the concept, the device structures and the fabrication techniques of strained-SOI CMOS. We introduce our original fabrication method of strained-SOI substrates, called the Ge condensation technique. It is experimentally shown that strained-SOI CMOS has higher electron and hole mobility and that strained-SOI CMOS ring oscillators successfully operate with the performance enhancement of 30-70% against conventional SOI CMOS ones. (C) 2003 Published by Elsevier B.V.