Implementation of strained SiGe in pMOSFETs provides up to 85% higher hole mobilities and 55% and 13% higher on-state currents for 10 mum and 70 nm channel lengths. Low leakage current, good Short Channel and Drain Induced Barrier Lowering behavior are obtained. Selective growth after standard shallow trench isolation (STI) allows deposition of the required channel material in the active pMOS region without negatively affecting the nMOS. It enables an easy integration of SiGe in standard CMOS technology, in contradiction to strained Si on strain relaxed buffers (SRBs). Our fabrication scheme offers a possible way to combine fully depleted CMOS devices with strained SiGe in pMOSFETs. (C) 2003 Elsevier B.V. All rights reserved.