Direct wafer bonding between high-density-plasma chemical vapour deposited (HDP-CVD) oxide and thermal oxide (TO) has been investigated. HDP-CVD oxides, about 230 nm in thickness, were deposited on Si(01 0 1) control wafers and the wafers of interest that contain a thin strained silicon (sSi) layer on a so-called virtual substrate that is composed of relaxed SiGe (similar to 4 mu m thick) on Si(0 0 1) wafers. The surfaces of the as-deposited HDP-CVD oxides on the Si control wafers were smooth with a root-mean-square (RMS) roughness of < 1 nm, which is sufficiently smooth for direct wafer bonding. The surfaces of the sSi/SiGe/Si(0 0 1) substrates show an RMS roughness of > 2 nm. After HDP-CVD oxide deposition on the sSi/SiGe/Si substrates, the RMS roughness of the oxide surfaces was also found to be the same, i.e., > 2 nm. To use these wafers for direct bonding the RMS roughness had to be reduced below 1 nm, which was carried out using a chemo-mechanical polishing (CMP) step. After bonding the HDP-CVD oxides to thermally oxidized handle wafers, the bonded interfaces were mostly bubble- and void-free for the silicon control and the sSi/SiGe/Si(0 0 1) wafers. The bonded wafer pairs were then annealed at higher temperatures up to 800 degrees C and the bonded interfaces were still found to be almost bubble- and void-free. Thus, HDP-CVD oxide is quite suitable for direct wafer bonding and layer transfer of ultrathin sSi layers on oxidized Si wafers for the fabrication of novel sSOI substrates. (c) 2006 Elsevier B.V. All rights reserved.