We propose a method of fabricating an offset-gated bottom gate polycrystalline-silicon (poly-Si) thin-film transistor (TFT) and a conventional one on one substrate. A successive etching process using the isotropy of wet etching is employed to self-align these structures without a high photolithographic step. According to the offset length the trade-off between the ON-state current and the leakage current is investigated. Experimental and simulated results indicate that the electrical properties of the proposed offset-gated TFT including a low leakage current compared with that of the conventional one by over two orders of magnitude are suitable for active matrix addressing elements. (C) 2007 The Electrochemical Society.