An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-V-CC negative-world-line DRAMs

Min KS; Kim YH; Kim D; Kim DM; Cho SI; Ahn JH; Chung JY

Current Applied Physics, Vol.3, No.6, 507-510, 2003

DOI10.1016/j.cap.2003.09.004 Export Citation

An 80% larger-current-output negative CMOS charge pump with 10% area penalty for sub-1-V-V-CC negative-world-line DRAMs

Min KS, Kim YH, Kim D, Kim DM, Cho SI, Ahn JH, Chung JY

A new CMOS negative charge pump scheme is proposed in this paper. This new pump scheme can generate output current which is 80% larger than the conventional pump with the sacrificial 10% area penalty. This new pump is regarded to be suitable to sub-1-V-V-CC DRAMs with the negative-word-line (NWL) scheme, where the dynamic current consumption is expected to be very large. (C) 2003 Elsevier B.V. All rights reserved.

Keywords:low-voltage charge pump;low-voltage generator;low-voltage circuit;negative word line;low-voltage DRAM circuit;low-voltage memory circuit;large-current-output charge pump