This paper describes novel low-power high-speed flip-flop called dual edge-triggered NAND keeper flip-flop (DETNKFF). The flip-flop achieves substantial power reduction by incorporating dual edge-triggered operation and eliminating redundant transitions. It also minimizes latency by reducing the height of transistor stack on the critical path. In addition, DETNKFF allows negative setup time to provide useful attribute of soft clock edge. Simulation results indicate that the proposed flip-flop reduces power consumption and latency by up to 56% and 28%, respectively, as compared to conventional flip-flops. For the typical input switching activity of 0.3, the power-delay product is also improved by as much as 61%. Synchronous counters were fabricated using a 0.35 mum CMOS technology. Experimental result indicates that the counter with DETNKFF saves overall power consumption by 48% and the layout area by 18% as compared to that with Hybrid latch flip-flop (HLFF). (C) 2003 Elsevier B.V. All rights reserved.