화학공학소재연구정보센터
Solid-State Electronics, Vol.45, No.7, 1107-1113, 2001
A novel experimental technique: combined gated-diode method for extracting lateral distribution of interface traps in SOI NMOSFETs
A novel method namely combined gated-diode technique for extracting lateral spatial distribution of interface traps induced by the electrically stressing is presented in this paper. This technique is based on the measurement of recombination-generation current characteristics via the modulation of the drain bias voltage of the forward gated-diode. The extracted results on the interface trap profile demonstrate that the induced interface trap density gradually decreases from the drain edge to channel region and shows the highest value near the drain edge.