Charge-loss effects in device dielectric strongly limit the reliability of non-volatile memory cells. The explanation of the leakage mechanisms is therefore an essential condition for the establishment of scaled and reliable technology for data storage, This paper concerns with the physical interpretation of the stress-induced leakage current (SILC), based on both experimental and computational investigations on MOS capacitor structures. It is found that: (a) the leakage is partly due to electron-hole recombination mechanisms in the bulk oxide, (b) defect levels acting as recombination- and trap-assisted tunneling (RTAT) sites are located at deep energy levels in the SiO2 and (c) the SILC characteristics of thin oxide (t(ox) < 8.5 nm) MOS samples can be very well reproduced by a numerical model featuring RTAT as the leading mechanism of the leakage. As a result, the oxide-degradation effects can be monitored by the new numerical tool.