To meet the market demand for LSI with even higher performance, traditional scaling has been pursued aggressively and has won great success towards 0.10 mum generations. To maintain continued growth in CMOS performance beyond 0.10 mum, key issues originating from the traditional scaling are addressed in this paper. With two-dimensionally optimized channel impurity profiles and innovative improvements of previous technologies such as ion implantation, thermal annealing, and alternative gate insulators, high performance sub-0.10 mum CMOS will be available. However, to meet a variety of market demands, equivalent scaling should be developed in addition to traditional scaling. (C) 2002 Elsevier Science Ltd. All rights reserved.