A model of ohmic connection through an n-type drain, metal, and a p-type drain in complementary metal-oxide-semiconductor (CMOS) inverters has been developed. This model is based on drift-diffusion (DD) transport, and in the model, the metal that connects nMOS and pMOS is replaced with an n(+) (or p(+)) low-resistance semiconductor. The diode formed between the n-type and p-type drains was designed to operate with an extremely low on-voltage above which current flows through forward-biased pn-junctions. To reduce V-on, we studied the relationship between V-on and the material parameters of the diode (e.g., carrier lifetime and band parameters). We found that V-on decreases with a decrease in carrier lifetime in a homogeneous material system but the minimum is a half of the band gap (similar toE(g)/2). By sandwiching narrow-gap semiconductors between the n- and p-type silicon regions, V-on can be reduced to smaller than a half of the band gap of the original material. When the band gap gradually narrows with multi-steps and a pn-junction is formed at the narrowest gap region with recombination centers, V-on drastically decreases (V-on << E-g) and the diode behaves like an ohmic resistor. When the n- and p-type drains are connected with a resistor-like diode, ohmic connection with low resistance can be achieved between nMOS and pMOS. The present modeling is validated by analyzing CMOS inverter operation. (C) 2002 Elsevier Science Ltd. All rights reserved.