The NOR cell arrays for the new dual floating gate (DFG) flash cells for multilevel operation are proposed. It was found that program disturb similar to the conventional stacked gate flash cell could be happened due to different amounts of charges stored in the two floating gates (FGs). Fortunately, it can be reduced significantly using the special memory array structure with the half-voltage programming technique, which employs the additional half-voltage bias on the control gates of unselected cells to prevent band-to-band tunneling generated hot holes injecting into the FGs. Simulation results indicate the new DFG flash cells are promising and practical for future multilevel flash memories. (C) 2002 Elsevier Science Ltd. All rights reserved.