Tail bits appearing during program/erase operation or after retention stresses are major threats to the floating-gate non-volatile memory reliability. Two-transistor (2T)-Fowler-Nordheim (FN)-NOR memories circumvent part of the tail bit induced problems of single transistor NOR and NAND configurations. However, the tail bits still represent a point of concern in the 2T-FN-NOR memory reliability, because of disturbs and stresses induced by application of the inhibition voltage and because of charge retention. In this paper the impact of tail bits in 2T-flash memory is investigated and it is suggested how to tackle this problem from design and process point of view. (C) 2002 Elsevier Science Ltd. All rights reserved.