In this paper physics-based numerical simulation is applied to the evaluation of the noise performance of MOS devices and circuits for technologies with minimum feature size ranging from 0.25 to 0.1 mum. Adopting a simulation approach for noise calculations that considers the transistor as an active transmission line and by post-processing the results of two-dimensional hydrodynamic device simulations, a detailed analysis of the dependences of MOSFET noise parameters and minimum noise figure (NF) on bias and technology scaling is carried out. Furthermore, the impact of scaling on the performance of a simple low noise amplifier is analyzed; analytical models and physics-based device simulations provide predictions about the trend of NF and power consumption of the amplifier, for operation frequencies from 900 MHz up to 20 GHz. The results of this work confirm that noise performance improve as CMOS technology is scaled down, increasing the interest for CMOS low-noise amplifiers. (C) 2002 Elsevier Science Ltd. All rights reserved.