We have investigated the influence of Si-cap thickness and Ge segregation on the device properties of Si/SiGe/Si heterostructure pMOSFETs to optimize the device design. It is found that the thermal gate-oxide quality is degraded abruptly during the Si-cap thinning because Ge segregation proceeds rapidly beyond a certain critical thickness. However, it is noted that the significant increase in interface state density (D-it) occurs only if the Ge concentration at the oxide interface is high enough (similar to1.8 x 10(22) cm(-3)). If D-it is kept low (<5.0 x 10(10) cm(-2) eV(-1)), a thinner Si cap improves device's transconductance, on-state current, threshold voltage, and subthreshold swing owing to the larger oxide-to-channel capacitance, less parallel channel effect, and higher degree of valence band bending. Finally, the Si-cap thickness should be controlled precisely to locate the buried channel as close as possible to the oxide as long as the minimum thickness for a low D-it is maintained. (C) 2002 Elsevier Science Ltd. All rights reserved.