The origins of different gate leakage behaviors for both PMOS and NNIOS with ultra-thin nitrided gate oxide have been studied and modeled. Both equivalent oxide thickness (EOT) and barrier lowering are affected the gate leakage. In NNIOS with nitrided oxide, the advantage of EOT decrease is larger to offset the barrier lowering, thus improvement on gate current reduction rate (R-Jg). The situation in PMOS is just contrary to the NMOS, therefore the gate leakage increased with increasing nitridation time. We attribute this to the different barrier lowering in conduction band and valence band. (C) 2002 Published by Elsevier Science Ltd.