This paper discusses the impact of the interconnect parameters on the signal delay of digital CMOS circuits. The minimum feature size for simulated MOSFETs was scaled in the range from 100 to 10 nm and interconnects were scaled down to 25 nm feature size. Our results show that new parasitic effects, as the size effect for copper and the increase of the threshold voltage due to direct tunneling gate current, will partly compensate the performance gain obtained by using new materials. These effects must be considered for minimum feature sizes below 50 nm. The influences have been studied on a logical unit and on on-chip interconnect scheme. (C) 2003 Elsevier Science Ltd. All rights reserved.