We have carried out extensive numerical modeling of nanoscale SOI MOSFETs in order to compare two basic options for ultimate scaling. Both devices are double-gate MOSFETs with ultra-thin undoped (intrinsic) channel, and highly doped electrodes; they differ only in the way the channel is connected to the source and drain. Transistors of the first type feature channels connected directly to elevated ("bulk") electrodes, while in MOSFETs of the second type the channel has thin doped extensions. Our numerical model of the devices takes into account the two most important factors limiting the device scaling, namely the gate field screening by source and drain, and quantum-mechanical source-to-drain tunneling along the channel. The results show that the decrease of the gate length L leads to a gradual device performance degradation, including voltage gain reduction, power dissipation increase, and (most importantly) an exponentially growing sensitivity to parameter variations. The degradation is comparable in devices of both types if L of transistors with thin channel extensions is in-between L and the channel length L-c = L + 2t(ox) (with oxide thickness t(ox)) of MOSFETs with bulk electrodes. However, the total ("bulk-to-bulk") length L-BB of the latter devices is always smaller than that of their thin-extension counterparts (at comparable performance), making the transistors with bulk electrodes the most preferable option for ultimate CMOS scaling. (C) 2004 Elsevier Ltd. All rights reserved.