Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate charge collection in Sol devices. Charge collection in capacitors and ICs can be induced by displacement currents caused by the release of charge in the substrate. The magnitude of charge collection depends on the geometry, gate surface area and oxide thickness of the device. It is mainly induced by the diffusion of carriers generated in the silicon bulk, which induces a voltage drop under the oxide surface. Carrier diffusion in low-doped silicon creates coupling effects between MOS elements separated by up to hundreds of microns. However, because of charge sharing effects, charge collection by displacement currents (by itself) does not appear to significantly affect SEU sensitivity in Sol devices. p-n junctions are far less sensitive to charge sharing effects than neighboring MOS structures. A mechanism that can significantly increase the SEU saturation cross section in SOI devices is charge release in non-ideally doped drain regions (not heavily doped throughout the silicon film). Carriers released in drain regions can drift or diffuse into the body region and be amplified by parasitic bipolar effects. By heavily doping drain junctions throughout the silicon film, drain strike sensitivity can be significantly reduced. For this case, SEU sensitivity can be limited to gate (body) strikes and by reducing parasitic bipolar effects using body ties, Sol circuits can be fabricated that are very hard to single event effects. These results have important implications on the soft-error reliability of SOI and other oxide-isolated structures, e.g., DRAMs. For Sol SRAMs, it is possible that the additive effects of charge collection by displacement currents and charge released in drain regions may lead to SEU. For trench DRAMs, the retention capacitors are particularly sensitive to charge released in the substrate. Charge collection in retention capacitors by displacement currents can lead to multiple bit upsets (MBUs) in DRAMs, thus significantly degrading the soft-error reliability of DRAMs. (C) 2004 Elsevier Ltd. All rights reserved.