Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design

Mitra S; Salman A; Ioannou DP; Tretz C; Ioannou DE

Solid-State Electronics, Vol.48, No.10-11, 1727-1732, 2004

DOI10.1016/j.sse.2004.05.006 Export Citation

Double gate (DG)-SOI ratioed logic with symmetric DG load - a novel approach for sub 50 nm low-voltage/low-power circuit design

Mitra S, Salman A, Ioannou DP, Tretz C, Ioannou DE

In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for low voltage/low power circuits. The logic gates are based on ratioed logic with depletion-mode (i.e., intrinsically on) Symmetric DG (SDG) load transistors and inversion-mode Asymmetric DG (ADG) driver transistors. Using this technique a basic inverter was designed, with better performance compared to "classical" CMOS DG design. This technique was extended to create a complete set of basic logic gates including NOR2, NAND2 and XOR2 gates. (C) 2004 Elsevier Ltd. All rights reserved.