In the sub-50-nm scale, the aggressive scaling of MOSFETs is expected to culminate in dual-gate (DG) architectures on Sol substrates. DG MOSFETs are widely accepted to be the ultimate design that silicon can deliver in terms of on and off currents. So far, the design efforts on these novel structures have concentrated on ideal geometries and doping profiles. However, at nanometer scale, devices fabricated with lithography and etching techniques cannot deliver perfect reproductions of the ideal design and suffer significantly from fluctuation effects associated with random doping and interfaces. While the former is less important in undoped, thin-body architecture, the interface roughness is a crucial factor in DG MOSFET performance, as indicated by the International Technology Roadmap for Semiconductors. Published by Elsevier Ltd.