The impact of emitter, inside spacer, and SIC lateral scaling on the AC and DC performance of a raised extrinsic base SiGe HBT has been investigated using the ISE TCAD simulation package and design of experiments methods. Strong first order effects for all three variables were observed while the interactions of the variables had a weaker effect. It was found that as the emitter size shrinks towards 0.1 mum the impact of changes to inside spacer and SIC width on the current gain increased. The response surface design led to an optimized simulated transistor featuring f(T) and f(MAX) values of 214 and 332 GHz, respectively. (C) 2004 Elsevier Ltd. All rights reserved.