This paper evaluates the effects of dimension variations on the latchup immunity of 0.18-mum CoSi2 shallow trench isolation (STI) CMOS structures. A comprehensive study on the test devices, by variations of geometrical dimensions as well as the spacings, has been established. Focus has also been given to the dimensions of the STI structure, mainly on the width and depth, as the rest of the parameters are varied. The influence of biasing condition on latchup has also been investigated. The results obtained and the as-developed characterization techniques shall bestow a CMOS device that promises optimized layout dimension. (C) 2004 Elsevier Ltd. All rights reserved.